RTL synthesis, place & route, static timing analysis, and native GUI viewers. Works exactly like Cadence Genus, Innovus, and Tempus. Free. Open source.
Same model as Cadence: separate tools, shared libraries, clean handoffs.
Reads Verilog RTL, runs technology-independent optimisation, maps to your standard cell library. Produces a gate-level netlist with timing and area reports.
Native Qt5 schematic viewer. Renders the mapped netlist as a gate-level schematic with real gate symbols (AND/NAND/OR/DFF/MUX), logic depth layout, and hierarchy browser.
Floorplanning, simulated-annealing placement with timing-driven net weights, H-tree clock distribution, congestion-aware global routing (MST + L-shape on M2/M3), DEF output.
Native Qt5 layout viewer. Dark canvas with cell colouring (green = combinational, blue = FF), per-layer routing visibility (M1/M2/M3/clock), zoom/pan, scale ruler, cell selection.
Standalone STA engine. Builds a timing graph from the mapped netlist, propagates arrival times using Liberty cell delays, reports WNS, TNS, critical path, and gives a PASS/FAIL timing check.
Works on Ubuntu 20.04+, Debian 11+, RHEL 8+, and any x86-64 Linux. GUI tools require libqt5widgets5.
Pre-built binaries. No compilation needed.
Installs all tools to /opt/ortus/bin/ and symlinks to /usr/local/bin/. For GUI tools, install Qt5 runtime first.
Ortus follows the same TCL command structure and tool flow used in professional EDA, great for students learning the field and engineers exploring open alternatives.
A complete physical design flow — no license server, no dongle, no annual renewal.
Synthesis, placement, and routing all implemented in C++17. Most designs complete in seconds, not hours.
Write .tcl scripts just like Genus or Innovus — or drop into the interactive shell by just typing the tool name.
agni-gui shows gate-level schematics. sutra-gui shows the placed & routed layout with per-layer visibility — like Innovus.
MST Steiner tree + 32×32 congestion grid. Chooses L-shape orientation to avoid hot spots. H-tree for clock nets.
Net weights from timing criticality feed into simulated annealing. Clock nets weighted 3× to minimise skew.
Ships with ortus_130nm and sky130_hd. Plug in any Liberty .lib from your foundry — TSMC, Samsung, SkyWater.
All reports — timing, area, placement, routing, slack — output as clean JSON for CI/CD and scripting.
No license server. No floating licenses. No call-home. Download, install, run on as many machines as you need.
Same professional workflow. Zero licensing cost.
| Feature | Synopsys (DC + ICC2 + PT) | Cadence (Genus + Innovus + Tempus) | Ortus EDA |
|---|---|---|---|
| RTL Synthesis | ✓ DC / Design Compiler | ✓ Genus | ✓ agni |
| Place & Route | ✓ IC Compiler 2 | ✓ Innovus | ✓ sutra |
| Static Timing Analysis | ✓ PrimeTime | ✓ Tempus | ✓ kala |
| Native layout GUI | ✓ IC Compiler GUI | ✓ Innovus GUI | ✓ sutra-gui (Qt5) |
| Schematic viewer | ✓ Design Vision | ✓ Genus GUI | ✓ agni-gui (Qt5) |
| TCL script flow | ✓ Yes | ✓ Yes | ✓ Yes |
| Liberty PDK support | ✓ Yes | ✓ Yes | ✓ Yes |
| Annual license cost | ✗ ~$1M+/yr | ✗ ~$1M+/yr | ✓ Free |
| Open source | ✗ No | ✗ No | ✓ Yes |
Pre-built binaries for Linux x86-64. No compilation required.
All five tools, ortus_130nm + sky130_hd PDKs, Examples, User guide, Install script