Ortus is an open, from-scratch EDA suite for Linux — RTL synthesis, place & route, and static timing in native C++. Each stage is checked against an independent tool, so the results can be reproduced, not taken on faith.
Ortus takes Verilog RTL to a placed, routed, timing-analyzed layout using three cooperating engines that share Liberty libraries and hand off through standard netlist and DEF formats — the same separation of concerns a professional flow uses.
agni synthesizes RTL to a gate-level netlist with real NPN truth-table technology mapping. sutra floorplans, places, and routes it on a real metal stack with well-tap and filler insertion and clock-tree synthesis. kala analyzes timing with a slew-aware, pin-specific delay model and reports worst and total negative slack.
It runs entirely on commodity Linux — no license server, no dongle, no annual renewal — and every capability ships with the script that proves it against an independent reference tool.
A complete physical-design flow you can download, install, and audit — with results you can verify yourself.
Synthesis, place & route, and static timing in one coherent suite — not a stitched-together collection of scripts.
Each stage is checked against an independent reference tool. The proof scripts ship in the box.
Batch TCL scripts for CI, or drop into an interactive shell by typing the tool name. JSON reports for pipelines.
Ships with sky130, gf180, and a 130 nm kit. Plug in your foundry's Liberty, LEF, and GDS — the flow is PDK-agnostic.
Everything is native C++17. Most designs complete in seconds, not hours — no cloud round-trip.
No floating licenses, no call-home, no renewal. Run it on as many machines as you need.
Every stage carries an independent reference — the same discipline a signoff flow uses. These numbers are measured on the open sky130 PDK and reproducible from the source tree.
Reproduce the whole scorecard with one command — bash scripts/prove_all.sh — given iverilog, OpenSTA, and Magic on your PATH.
Each tool is a standalone binary with an interactive shell and a scriptable batch mode.
Reads Verilog, runs technology-independent optimization, and maps to your standard-cell library with real NPN truth-table matching — not naive operator substitution. Produces a gate-level netlist with timing, area, and power reports, plus a native Qt5 schematic viewer (agni-gui).
Floorplanning, simulated-annealing placement with timing-driven net weights, well-tap and filler insertion, H-tree clock-tree synthesis, and congestion-aware routing on a real metal stack. Writes DEF and GDS, with a native Qt5 layout viewer (sutra-gui) offering per-layer visibility.
Builds a timing graph from the netlist and propagates slew-aware NLDM delays with pin-specific arcs, reporting worst and total negative slack, Fmax, and the critical path. Supports SPEF back-annotation, clock uncertainty, false and multicycle paths, and multi-corner PVT analysis.
Install, run the full RTL-to-GDS flow, and reference every command — verified against the shipping binaries.
Pre-built binaries for x86-64 Linux (Ubuntu 20.04+, Debian 11+, RHEL 8+). GUI viewers need the Qt5 runtime. No compilation required.
Each stage is a short script that reads the previous stage's output. The uart_tx example runs end to end, and every command shown is the real vocabulary the binaries dispatch — run agni -f synth.tcl, kala -f sta.tcl, sutra -f pnr.tcl from the example directory.
Ortus reads standard Liberty .lib for timing and LEF for geometry, so any PDK works. For sky130 the open files are one command away; full foundry signoff decks come from volare.
The three shells share one dispatch, so a command works in whichever tool the stage belongs to. These are the actual command names — run any script with -f, or type them at the interactive prompt. Select a tool.
| Run | |
| agni -f synth.tcl | Run a synthesis script (the shipped flow). |
| agni auto | Autonomous closed loop — RTL to layout, choosing each next move from measured results. |
| Synthesis shell | |
| set_pdk / read_builtin_lib | Select the PDK and load its cell library. |
| read_verilog / elaborate | Read RTL and elaborate the top module. |
| read_liberty | Load a Liberty timing library (a foundry corner). |
| read_sdc / create_clock | Load constraints, or define the clock (ps). |
| set_max_fanout / set_max_transition | Design-rule limits for mapping. |
| compile_ultra | Technology-independent optimization, then map to cells. |
| report_area / report_timing / report_qor / report_power | Post-synthesis reports. |
| write_verilog / write_sdc | Write the mapped netlist and constraints. |
| Setup | |
| read_verilog / set_top_module | Gate-level netlist from agni, and the top cell. |
| set_pdk / read_liberty | PDK rules and Liberty library (or read_builtin_lib). |
| read_lef | Tech + cell LEF — real pin and via geometry. |
| read_sdc / create_clock | Constraints, or the clock (ps). |
| Floorplan · place · route | |
| init_floorplan | Auto-size the die: -utilization or -die_width -die_height. |
| create_power_plan | Power rings, stripes, and follow-pin rails. |
| place_design | Analytical + legalized placement (-effort). |
| insert_tap_cells | Stamp well-taps on the latch-up pitch. |
| clock_tree_synthesis | Build the balanced clock H-tree. |
| route_design | Global + detailed grid routing. |
| optimize_vias | Redundant vias where DRC-legal (off by default). |
| insert_fillers | Fill row gaps with filler / decap cells. |
| Signoff · output | |
| run_drc / report_drc | Native DRC predictor — fast, not signoff. |
| write_def / write_spef / write_gds | Layout, parasitics, and mask geometry. |
| write_spice | Schematic netlist for LVS. |
| signoff -dir | Drive Magic DRC + Netgen LVS → signoff.json. |
| Setup | |
| read_verilog / set_top_module | Gate-level netlist and top cell. |
| set_pdk / read_liberty | PDK and Liberty timing library (or read_builtin_lib). |
| read_spef | Back-annotate wire RC from SPEF. |
| Constraints | |
| read_sdc / create_clock | Load an SDC, or define the clock (ps). |
| set_clock_uncertainty | Setup jitter / uncertainty. |
| set_false_path | Exclude a path. -from -to |
| set_multicycle_path | N-cycle path. -setup N -from -to |
| set_input_delay / set_output_delay | IO timing budgets. |
| Analysis | |
| update_timing | Propagate arrivals / required times. |
| report_timing | Critical paths. -nworst N -hold -max_paths N |
| report_global_timing / report_clock_timing | WNS / TNS summary and clock report. |
| check_timing | Unconstrained / unclocked checks. |
The proof scripts check each stage against its reference tool and print one scorecard. Requires iverilog, OpenSTA, and — for physical signoff — Magic + Netgen with a PDK on PATH.
Ortus is younger and smaller than the incumbents — and honest about it. Here is the map.
| Capability | Synopsys | Cadence | Ortus |
|---|---|---|---|
| RTL synthesis | Design Compiler | Genus | agni |
| Place & route | IC Compiler 2 | Innovus | sutra |
| Static timing | PrimeTime | Tempus | kala |
| Schematic + layout GUI | Yes | Yes | Yes — Qt5 |
| TCL script flow | Yes | Yes | Yes |
| Reference-checked claims | internal | internal | public scripts |
| Signoff flow (Magic DRC + Netgen LVS) | built-in | built-in | integrated |
| DRC / LVS signoff-clean at scale | Yes — mature | Yes — mature | in progress |
| Annual license | $1M+/yr | $1M+/yr | Free |
| Open source | No | No | Yes |
Install, run your first RTL-to-GDS flow, and read the command reference for all three tools.
Read the docs →Full source for the engines, the example designs, and the reference-check proof scripts.
View source →Each stage checked against iverilog, OpenSTA, and Magic — reproducible from one script.
See the numbers →Pre-built binaries for Linux x86-64. No compilation required.
All tools, sky130_hd + ortus_130nm + gf180mcu PDKs, examples, and the install script.